The Tektronix MSO2000, MSO3000, MSO4000, and MSO5000 Series of mixed signal oscilloscopes combine the uncompromised performance of a Tektronix oscilloscope with the basic functionality of a 16-channel logic analyzer, including parallel/serial bus protocol decoding and triggering. The Tektronix MDO4000 Series adds a dedicated RF input to the MSO Series platform to provide a built-in spectrum analyzer. The MSO Series is the tool of choice for quickly debugging digital circuits using its powerful digital triggering, high resolution acquisition capability, and analysis tools. This application note focuses on verification and debugging tips to help you become more efficient in implementing your digital designs using the Tektronix MSO Series.

A mixed signal oscilloscope’s digital channels view a digital signal as either a logic high or logic low, just like a digital circuit views the signal. This means as long as ringing, overshoot and ground bounce do not cause logic transitions, these analog characteristics are not of concern to the MSO. Just like a logic analyzer, an MSO uses a threshold voltage to determine if the signal is logic high or logic low. The MSO5000, MSO4000 and MDO4000 Series provides perchannel threshold settings that are useful in debugging circuits with mixed logic families. Figure 1 shows the MSO4000B measuring five logic signals on one of its digital probe pods. Three TTL (Transistor-Transistor Logic) signals and two LVPECL (Low-Voltage Positive Emitter-Coupled Logic) signals are measured at the same time.

There are two major digital acquisition techniques. The first technique is timing acquisition in which the MSO samples the digital signal at uniformly spaced times determined by the MSO’s sample rate.
At each sample point, the MSO stores the signal’s logic state and creates a timing diagram of the signal. The second digital acquisition technique is state acquisition. State acquisition defines special times that the digital signal’s logic state is valid and stable.

This is common in synchronous and clocked digital circuits. A clock signal defines the time when the signal state is valid. For example, the input signal stable time is around the rising clock edge for a D-Flip-Flop with rising edge clocking. The output signal stable time is around the falling clock edge for a D-Flip-Flop with rising edge clocking. Since the clock period of a synchronous circuit may not be fixed, the time between state acquisitions may not be uniform as it is in a timing acquisition.

The Tektronix MSO Series simultaneously decodes up to two to sixteen buses, depending on the model. The buses are defined as parallel or serial (I2 C, SPI, USB, CAN, LIN, FlexRay, RS-232/422/485/UART, Ethernet, MIL-STD-1553, and I2 S/LJ/ RJ/TDM). The parallel bus is composed of any of the digital channels D0 through D15. The serial bus is composed of any of the analog channels 1 through 4 and the digital channels D0 through D15. The MSO2000, MSO3000, MSO4000 and MDO4000 Series provides maximum design visibility by displaying up to four analog channels, four reference waveforms, one Math waveform, four buses and 16 digital channels at one time. The MSO5000 Series provides even greater analysis capabilities, with up to four Math waveforms and sixteen buses at once.